RTSS: uma família de técnicas de leitura para suporte à inspeção de modelos SysML e Simulink - Antonio, Erik Aceiro (Universidade Federal de São Carlos, 2014)
Context: Usually, developers of Embedded Systems (ESs) start the development from models next to the code generation phase, for example, SysML diagrams and Simulink models. Despite the whole use of these models by the ES community, there is a lack of Verification and Validation activities (V&V). The certification standards operate, mainly, on code level. Aim:to define a family of reading techniques Reading Techniques for SysML and Simulink (RTSS) that supports the inspection of these diagrams and models, aiming to improve the process and product quality through defects identification, as soon as artifacts are elaborated. Method: the reading techniques were defined based on a systematic process and they support pairs of artifacts. They take some international certification standards into account, as well as elements from the structure of SysML and Simulink languages. Besides, aiming to suggest the use of these techniques inside a development process, the SYSMOD process was took as reference, since it adopts SysML diagrams and Simulink models along its phases. For evaluating the RTSS techniques two controlled experiments and three case studies were conducted as the techniques were elaborated. Results: the results showed that it is feasible to use the techniques and that they are able to detect defects on the pair of artifacts for the ones they were designed. In addition, it was observed that defects that were not identified and corrected inside the phase they were generated, were propagated to the subsequent phases. Conclusion: Based on these results, we can conclude that the RTSS techniques are able to detect defects as the artifacts are elaborated, avoiding their propagation to further phases. This fact can improve both the process and the product besides minimize the rework and the cost of correcting defects in further phases. Finally, we observed that the techniques can be applied even the SYSMOD process is not being used. In this case, it is enough that the pair of artifacts dialed by each technique is available.
Keywords: Validação, verificação e teste; Sistemas embarcados; SysML (Sistema de computador); SIMULINK (Programa de computador); Técnicas de leitura; Embedded systems; Simulink; Reading technique; Verification and validation; SYSMOD; Development process; CIENCIAS EXATAS E DA TERRA::CIENCIA DA COMPUTACAO