Simulador de alto nível para network-on-chip: método para a exploração de estratégias de mapeamento e roteamento - Paris, Paulo Cesar Donizeti (Universidade Federal de São Carlos, 2024)
Many-core architectures can contain dozens or even hundreds of processing cores on a single chip, being used in high-performance applications due to their parallel execution capability. Although they offer great potential for task-level parallelism, they face challenges, particularly in the efficient division and communication among tasks. Communication among cores is essential, especially with the use of Network-on-Chip (NoC), which aims to solve scalability and energy efficiency issues. This paves the way for optimizing these approaches, both in terms of hardware support and mapping and routing strategies. Several specific simulators for NoCs have been developed to evaluate and optimize this potential. However, the majority are complex, operating at lower levels of the architecture, such as in the functional and performance characteristics of routers, and do not encompass mapping strategies. While they are excellent specialized tools, they offer little flexibility, being suited to specific scenarios or fixed configurations. This can create a demand for simpler comparative studies, with a lower learning curve and greater flexibility. To complement these efforts and fill possible gaps, this thesis proposes a method for exploring high-level mapping and routing strategies, called the NoC Simulator. This approach enables initial studies and comparisons of many-core designs, including customizable optimization algorithms for mapping parallel tasks of arbitrary complexity, as well as routing algorithms. With its simplified and modular approach, the proposed simulator allows users to distinguish each process of the simulation, from parameter configuration to performance metric evaluation, focusing on energy consumption. Experimental results confirmed its reliability in estimating simplified energy consumption, demonstrating its utility for design space exploration analyses and comparisons among different mapping and routing strategies. Thus, it constitutes an interesting approach for teaching and research activities in the field.
High-level simulator for network-on-chip: method for exploring mapping and routing strategies
Keywords: Many-core; Network-on-chip; Mapeamento de aplicações; Algoritmos de mapeamento; Algoritmos de roteamento; Simuladores para NoC; Métrica de consumo energético; Application mapping; Mapping algorithms; Routing algorithms; NoC simulators; Energy consumption metrics; CIENCIAS EXATAS E DA TERRA::CIENCIA DA COMPUTACAO::METODOLOGIA E TECNICAS DA COMPUTACAO