Implementação de um ambiente de verificação funcional UVM em Python aplicado ao fluxo de design digital SKY130

Abstract

The democratization of integrated circuit development enabled by open-source tools still finds one of its main obstacles in functional verification. This work investigates the feasibility of a Python-based verification flow applied to advanced stages of digital design, including functional coverage, structural code coverage, post-layout simulation, and power estimation. To evaluate this approach, a complete verification environment was developed for a serial communication controller widely used in embedded systems, using an open integrated circuit manufacturing technology as the reference platform. The results demonstrate that the proposed approach is capable of validating the design across different abstraction levels while achieving high coverage and producing consistent power consumption estimates. The experiments indicate that the integration of the Python ecosystem with open-source tools represents a viable, accessible, and sufficiently robust alternative for research, education, and integrated circuit development.