Simulador educacional de NoC: visualização do funcionamento da rede e estudo de algoritmos de mapeamento

Abstract

In the literature, several simulators for Many-Core processors and Network-on-Chip (NoC) architectures have been proposed. However, most of these tools present a high level of complexity, requiring advanced knowledge of low-level hardware concepts, which makes them unsuitable for undergraduate students, especially in early stages. Furthermore, there is a lack of accessible simulators developed in high-level programming languages such as Python. This work presents the development of an educational simulator for Many-Core systems based on NoC architectures, focusing on accessibility and usability without compromising the accuracy of performance analysis. The proposed simulator abstracts key structural and functional aspects of NoCs, including topology configuration, packet management, routing algorithms, and performance metrics such as latency, energy consumption, and fault tolerance. Additionally, the tool provides support for task mapping algorithms and enables intuitive interaction through a graphical interface, allowing users to visualize system behavior dynamically. The simulator was validated by comparing its results with baseline studies from the literature, demonstrating similar performance trends. The proposed approach contributes to the democratization of access to NoC simulation tools, offering an effective platform for teaching and experimentation in undergraduate Computer Engineering courses.