Análise de desempenho de Pipeline em processadores RISC-V implementados em FPGA

Abstract

In the current hardware development scenario, there are several types of processors on the market, each with specific configurations that meet different performance, power consumption and complexity needs. The RISC-V architecture emerges as a modular and flexible solution, allowing the adaptation of the number of pipeline stages and the inclusion of optimizations according to the desired application. This work analyzes the impact of different pipeline configurations and optimizations, such as bypass and early branch, on performance, power consumption and logical resource use in VexRiscv-based processors, a highly configurable implementation of the RISC-V architecture. Processors with two, three and four stages of pipeline were evaluated, considering operations with and without multiplication. The results show that processors with more stages, offer higher performance when they are active optimizations, but with a significant increase in energy consumption and resource use. Three-stage processors have an ideal balance between performance and power consumption, while two-stage processors stand out for simplicity and lower power consumption but with reduced performance. The activation of bypass and early branch has been shown to significantly improve performance, especially in complex operations such as multiplication, but with an additional cost in terms of energy consumption and resources. The analysis also revealed that the inclusion of multiplication increases energy and resource consumption, but pipeline optimizations offset this increase by improving processor efficiency. This study reinforces the importance of understanding these trade-offs to optimize the performance and efficiency of embedded systems and high performance, highlighting the versatility of RISC-architectureV and the VexRiscv core as powerful tools for custom hardware development.