Implementação de extensões criptográficas no processador VexRiscv

Abstract

This work presents the design, implementation, and evaluation of a set of bit-manipulation instructions from the cryptographic extension Zbk(b/c/x) of the RISC-V standard, integrated into the VexRiscv processor and synthesized on an FPGA. To validate correctness and quantify performance improvements, a dedicated testing framework was developed to systematically compare the hardware-accelerated instructions with their software-based counterparts, measuring latency, functional equivalence, and overall speedup across diverse input vectors. Experimental results show substantial acceleration, ranging from 2× in simple logical operations to over 100× in polynomial multiplication instructions over finite fields. The integration into the VexRiscv pipeline proved technically feasible, maintaining compatibility with the LiteX ecosystem and preserving the number of cycles per instruction in unrelated operations. These findings indicate that cryptographic extensions in the RISC-V standard can deliver significant benefits even on compact microarchitectures, reinforcing their suitability for configurable and energy-efficient SoCs.