Bit-True simulation for word length optimization of digital signal processing blocks

Abstract

During the development of DSP systems to be implemented in ASICs or FPGAs, the conversion of floating-point signals and operands to fixed-point is an important and time consuming task, as fixed-point has faster performance and lower power consumption. However, the floating-point to fixed-point conversion problem is NP-hard and has no ideal solution. This work explores a hardware simulation technique, also known as Bit true, based on masking the fractional bits of each operator and signal of interest directly in its FPGA implementation. This technique had only been proposed in the literature but never implemented before this work. It allows flexibility in defining optimization criteria and avoids the rework required by other techniques of implementing the system f irst in software, and only then transforming it into an equivalent hardware architecture. The DSP system chosen as a case study is a wireless BPSK receiver, designed for IoT applications. The receiver blocks were optimized in isolation using the technique, resulting in reduced area and power consumption, and increased maximum operating frequency. The artifacts produced in this work are expected to aid future research in IoT, reducing the time and effort to obtain a refined system systhesis.